Intel executives have long showed slides that illustrate its progress in shrinking transistors on chips, featuring nearly identical fever lines as new generations of production technology are perfected. The chart William Holt produced at a recent analyst meeting didn’t look right.
Ordinarily, Intel slides show a smooth upward curve, indicating that a small number of defects on chips gradually decline to nearly zero–as happened when Intel’s current manufacturing recipe was refined. But the line Holt showed for the successor technology started with a much smaller yield of good chips, and actually got worse for several months before Intel engineers began to get defect problems under control.
Intel had said in mid-October that the new process would be delayed three months, a blemish on its steady two-year pace observing what the industry calls Moore’s Law. But the company did not then say why.
Holt, the executive vice president in charge of Intel’s manufacturing operations, for the first time laid the blame at yield problems. He added that such a hiccup is rare but not unprecedented at the company.
“It’s the first time in quite a number of generations,” said Holt. “It’s just getting really hard.”
Read more about the challenge of keeping up with Moore's Law at The Wall Street Journal.
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